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Entities and Architectures
Entities and architectures are
the highest level objects in GM VHDL. Together they specify the
interface and behavior of a design. A GM VHDL source file may contain
entity, architecture, configuration, and package declarations (configuration
and package declarations will be discussed in the next chapter). For every
entity in a
source file there must be at least one corresponding architecture for
that entity in the same file. Furthermore, all architectures
corresponding to a particular entity must be in the same file with
that entity declaration. So a complete source file could contain just
one entity declaration and one or more architecture declarations for that
entity. The examples of the half adder taken together in one file would be a
complete design file.
Entities
Architectures