Discrete event simulation

Once a design has be specified in GM VHDL, it can be simulated or executed. GM VHDL uses a discrete event time model of execution. This means that the values of outputs are only computed at particular times when necessary. More precisely, an output value is only computed if a value upon which it depends has changed. This is in contrast to simulators for analog circuits which solve for the values of outputs over a continuous time interval. The GM VHDL data object used to represent the values of hardware signals is called a signal. If a signal's value is recomputed, then a transaction is said to have occurred on that signal. If, as the result of a transaction on a signal, the value of that signal is changed, then an event is scheduled to occur at the current time or some time in the future that will result in assigning the new value to the signal.

When any given signal changes, it might cause other signals to change, which might in turn cause more signals to change, and so on. The process by which values are propagated in this manner is performed by a kernel. The kernel for GM VHDL is provided by the two loaders in the package. When a simulation is started, the kernel sets the initial values of all the signals in the design being simulated. Next, the kernel executes each process once. Then the kernel repetitively performs a simulation cycle.

The purpose of the simulation cycle is to maintain the schedule of events. At the beginning of the simulation cycle the time is advanced to the time of the earliest scheduled event. Then all events scheduled for the current time are executed. Then, any processes that are sensitive to signals that have had an event resume execution until the process suspends again. The simulation cycle is repeated until the list of scheduled events is empty and no processes can be resumed or time reaches its highest value (time'high).