Data Flow

In this section, we will define a new description of the half adder using the data flow method. Since it is sometimes useful to have more than one model for a given part, an entity is allowed to have more than one architecture defined for it. Thus, we can declare a new architecture for the same entity declaration used in the last section. A data flow architecture body for the half adder might be This is much more concise then the structural model. It contains two statements that describe how data flows from a and b to s and c by assigning s and c the values of expressions involving a and b. These statements are called concurrent signal assignment statements. The expressions on the right-hand side of the signal assignment operator, <=, use the built in operators xor and and for objects of the type bit.

This is a purely functional description of the half adder, since the value of a xor b and a and b are assigned to s and c instantaneously when a or b changes. A description that uses timing can also be described by adding a delay to the assignment of the new values. Suppose each gate had a 1ns delay, then we could write our model Now, if a change to a or b causes the value of s or c to change, then that change will not occur until 1ns after the change in a or b. Timing can also be used in the structural description of the last section, but it would be part of the description of the and and xor components so that any time one of the gates was used, it would have the delay built in.