The definition of a design in GM VHDL requires two parts, an entity and an architecture. The entity declaration describes the inputs and outputs of the design. The description of the inputs and outputs is called the interface and is analogous to a pin list you might find in a data book. The architecture declaration actually describes the operation of the design.
We begin the design of the half adder with the entity declaration that defines the interface to the half adder. The entity declaration is The first and last lines mark the start and end of the declaration and assign a name to the design. The middle section is called a port clause and defines the inputs and outputs (called ports). On the first line, the ports a and b are defined to be of the mode in (inputs). Bit is called the type of the port and defines what kind of objects a and b are. The bit type is an object that can have the values '0' or '1' and represents a digital signal. The next line defines s and c to be ports of mode out (outputs), also of the type bit. The entity declaration can contain more than just the definition of inputs and outputs, but for now we will just use the port clause.
Now we need to declare an architecture that describes the operation of the half adder. The declaration for the half adder is This is a structural description of the half adder. The first line defines a name for the architecture and specifies that this is a model for the half_adder design. The next section is called the declaration part and is used to declare any items that we need to use in the description of the model. In this architecture, two components are declared that will be used to build the adder. These declarations specify the interface of the components we wish to use in the same way we specified the interface in the entity declaration of the adder. This corresponds to picking out which parts to use in the TTL analogy. Since we did not specify what entities describe the behavior of the and and xor components, the compiler will assume there are entities declared elsewhere with the same name as the components (i.e. and and xor).
The BEGIN statement marks the end of the declarative region and the beginning of the architecture body. The architecture body contains the actual description of the operation of the design. The architecture body in this example contains two component instantiation statements. In the TTL analogy a component instantiation corresponds to actually buying a TTL part (an instance) and placing it on the bread board. The first line of the instantiation defines a name for the instance being instantiated and the name of the part begin instantiated. The second line of the instantiation corresponds to the wiring process in the TTL analogy. The port map defines how signals should be mapped (connected) to the inputs and outputs of the part being instantiated. The port map of sum, maps the inputs of the half adder to the inputs of the xor gate and the output of the gate to the sum output of the half adder. The port map of carry, maps the inputs of the half adder to the inputs of the and gate and the outputs of the gate to the carry output of the half adder.