The logical operators NOT, AND, OR, NAND, NOR, and XOR can be used with any bit type or bit_vector. When used as operators on bits they have their usual meaning. When used with bit_vectors, the bit_vectors must have the same number of elements, and the operation is performed bitwise. For example, "00101001" xor "1110101" results in "11001100".
note: just as '0' and '1' represent constant bit values, constant
bit_vectors
can be written in VHDL as a list of bit values in double quotes. For example,
if d is a bit_vector(1 to 4) the following statement gives d the permanent
values d(1)='1', d(2)='1', d(3)='0', and d(4)='0'.
d<="1100";
Hexadecimal can also be used as a shortcut as in the following example.
d<=X"C";
Since C is the hexadecimal number 12, which in binary is 1100, this statement
is equivalent to the one preceeding it. The X in the front indicates that
the number is in hexadecimal instead of the normal binary.
The typical algebraic operators are available for integers, such as +,-,* (multilication), and / (division). Although these operations are not built-in for bit_vectors, they are often provided in libraries that come with your VHDL software. They are used with bit_vectors by interpreting them as a binary representation of integers, which may be added, subtracted, multiplied, or divided.
Also predefined are the normal relational operators. They are =, /=, <, <=, > and >= and have their usual meanings (/= denotes the not equal operator). The result of all these operators is a boolean value (TRUE or FALSE). The arguments to the = and /= operators may be of any type. The arguments of the <, <=, > and >= operators may be any scalar type (integer, real, and physical types) or the bit_vector type. If the arguments are bit_vectors, then the arguments must be the same length and the result is TRUE only if the relation is true for each corresponding element of the array arguments.
The & operator is a built-in VHDL operator that performs the concatenation of bit_vectors. For example, with the following declarations:
signal a: bit_vector (1 to 4); signal b: bit_vector (1 to 8);The following statement would connect a to the right half of b and make the left half of b constant '0'.
b<="0000" & a;The & appends the a to the end of the "0000" to form a result that contains 8 bits.
The previous section is Data Flow Descriptions - Other
Types.
The next section is Data Flow Descriptions - Signal
Assignments.