Source Code - hc11clk.vhd

n Source Code - hc11clk.vhd file: hc11clk.vhd
--
-- Motorola HC11 VHDL model
-- Copyright (C) Green Mountain Computing Systems, 1995
-- All rights reserved.
--
-- This software is provided "as is" without warranty of any kind.  Green 
-- Mountain Computing Systems does not accept any responsibility for results
-- obtained by using this software and does not guarantee that the software
-- is correct.
--
-- hc11clk.vhd : This is the VHDL behavioral implementation of the HC11
--        internal and external clocks.
--
-- 5/25/95 : Created - Scott Thibault
--

-- The clock entity generates all internal and external clocks using the
-- cycle time of an external clock.  The Tcycle generic defines the cycle
-- type of the external clock.  The ph1,ph2, and ptaclk are internal clocks
-- used throughout the reference manual.

entity clock is
  generic (Tcycle : time := 83.25ns);
  port (extal,E: out bit;
        ph1,ph2,as: out bit;
        ptaclk: out bit);
end clock;

architecture behavoir of clock is
  constant Thalf : time :=Tcycle/2;
begin
  gen_extal: process
  begin
    extal<='0','1' after Thalf;
    wait for Tcycle;
  end process;

  gen_clock: process
  begin
    -- main HC11 clock is extal/4
    E<='0','1' after Tcycle*2;
    -- ph2 is E shifted 90 degrees
    ph2<='0','1' after Tcycle,'0' after Tcycle*3;
    -- ph1 is ph2 inverted
    ph1<='1','0' after Tcycle,'1' after Tcycle*3;
    -- address strobe
    as<='0','1' after Thalf,'0' after Thalf*3;
    -- clock reference for port A pin logic
    ptaclk<='1','0' after Tcycle;
    wait for Tcycle*4;
  end process;
end behavoir;
type b to return to text