Modules and compatibility

Many existing VHDL compilers do not treat libraries in the same way as described in the last section. For this very reason, a utility program called vlib can be used to remain compatible with other tools. Many other tools compile several VHDL design files into one library file, as opposed to having one library file for every VHDL design file as with GM VHDL. The vlib utility allows you to "combine" several object files into one library file. The vlib utility can be used in two ways. First to add the contents of an object file into a library file use: The library filename must have a .lib extension. If the library file does not exist it will be created. The second use is to remove an object-file from a library. This can be done with the command: Thus to compile all designs into a library called work (as many tools do), after compiling a design file, add it to the work library with the vlib utility.

WARNING, the vlib utility does not actual put the contents of an object file into the library file, but rather puts a reference to the object file in the library file. This means that if the object file is changed, the library file will refer to the updated object file. Also, the object file must still exist and be in one of the VHDLPATH or current directories, in order to use the library file.