A single event is specified by the time at which the event is to occur followed by a space and the new value of the waveform. The time value is written as a VHDL time literal (i.e. a number followed by a valid predefined time unit name). The value is specified as an integer (for enumeration types, the value is the position number of the enumeration element) For example, suppose we wish to describe the following bit waveform.
.----. .----------------------------------- | | | ----' `---------------' 10ns 20ns 50nsSince the bit is an enumeration type, you need to use the corresponding integer of its elements instead of '0' and '1'. These would be 0 for '0' and 1 for the '1' because the '0' is first in the enumeration type and '1' is second. Thus a waveform file for the waveform above would look like:
0ns 0 10ns 1 20ns 0 50ns 1Another more interesting example of how elements of an enumeration type map to integers is the std_ulogic type of the standard IEEE library. The std_ulogic enumeration type is declared as
TYPE std_ulogic IS ( 'U', -- Uninitialized 'X', -- Forcing Unknown '0', -- Forcing 0 '1', -- Forcing 1 'Z', -- High Impedance 'W', -- Weak Unknown 'L', -- Weak 0 'H', -- Weak 1 '-' -- Don't care );The following table lists how the elements of the std_logic type would be mapped to integers.
Element Corresponding Integer --------------------- 'U' 0 'X' 1 '0' 2 '1' 3 'Z' 4 'W' 5 'L' 6 'H' 7 '-' 8A periodic event can be specified by a periodic equation followed by at least one space or tab and the value to be applied to the waveform. The periodic equation should be of the form a+bx, where a and b are time values and x is the literal character x. The command will cause the event to occur at times a+bx, for x=0,1,2,3,... In other words a is the first time which the event occurs, and there after the event will occur every b time units. For example, a clock of the std_ulogic type (described above), which starts at 100ns and has a period of 10ns, could be specified by the following waveform commands.
100ns+10ns x 2 105ns+10ns x 3The first line describes the falling edges of the clock. The clock starts at '0' at time 100ns, the clock is then '0' every 10ns there after (i.e. 110ns, 120ns, ...). Remember the number 2 is the corresponding integer for the '0' element of the std_ulogic type. The second line describes the rising edges of the clock. The clock starts at '0' so the first rising edge is at 105ns (for a 50% duty cycle), there after the clock rises every 10ns (i.e. 115ns, 125ns, ...). Remember the number 3 is the corresponding integer for the '1' element of the std_ulogic type. We also might add the line
0ns 0to specify that our clock is 'U' (uninitialized) to begin with.
You may also use integer valued waveform files for signals/variables of the bit_vector type. The integer value is converted to a n digit base 2 number, where n is the length of the vector. The values of the these digits from the MSB to the LSB are applied to the vector from left to right. For example, the following waveform
0ns 0 1ns 1 2ns 4 3ns 3applied to a vector a declared as a bit_vector(2 downto 0), would result in the following waveform for a.
.---------. a(2) ---------------------' `--------- .--------- a(1) -------------------------------' .---------. .--------- a(0) -----------' `---------' 0ns 1ns 2ns 3nsAn example of a complete waveform file for the bit type might be
0ns 0 500ns+100ns x 0 566ns+100ns x 1This would be used to represent a clock that is initially zero, doesn't begin running until time=500ns, has a 100ns cycle time and 33% duty cycle.