Contents Up << >>
Green Mountain VHDL vs. IEEE VHDL
This chapter describes the differences between Green Mountain VHDL and
the IEEE Std 1076-1993 VHDL specification. GM VHDL vs. IEEE standard:
-
Attribute specifications in configurations are not supported.
-
Configurations can only be used to configure architectures. The standard also
allows the configuration of blocks, and generate statements.
-
There is no run-time range checking on scalar type objects. In the standard,
it is an error if, during execution, a scalar object takes a value out of
its subtype range.
-
Case statements do not need to be exhaustive, provided the unspecified cases do
not occur during execution. The standard requires that every case be
specified.
-
With the exception of vectors, a sub-element of a composite type can not be a
resolved subtype. There is no related restriction in the standard.
-
Signals may not be declared in packages. There is no related restriction in
the standard.
-
Ports of the top-level entity must not be of a resolved type.
-
Resolved port actuals can only be associated with formals of the same resolved
type.
-
Port signals of an array type must be constrained.
-
Objects of resolved array types may only be assigned using whole array
assignment.
-
Wait statements in subprograms can not reference signal parameters.
-
Conversion functions may not be used in port actuals.
-
The extended aliasing features of VHDL'93 are not supported.
-
The groups, reject and postponed features of VHDL'93 are not supported.