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Green Mountain VHDL vs. IEEE VHDL

This chapter describes the differences between Green Mountain VHDL and the IEEE Std 1076-1993 VHDL specification. GM VHDL vs. IEEE standard:
  1. Attribute specifications in configurations are not supported.
  2. Configurations can only be used to configure architectures. The standard also allows the configuration of blocks, and generate statements.
  3. There is no run-time range checking on scalar type objects. In the standard, it is an error if, during execution, a scalar object takes a value out of its subtype range.
  4. Case statements do not need to be exhaustive, provided the unspecified cases do not occur during execution. The standard requires that every case be specified.
  5. With the exception of vectors, a sub-element of a composite type can not be a resolved subtype. There is no related restriction in the standard.
  6. Signals may not be declared in packages. There is no related restriction in the standard.
  7. Ports of the top-level entity must not be of a resolved type.
  8. Resolved port actuals can only be associated with formals of the same resolved type.
  9. Port signals of an array type must be constrained.
  10. Objects of resolved array types may only be assigned using whole array assignment.
  11. Wait statements in subprograms can not reference signal parameters.
  12. Conversion functions may not be used in port actuals.
  13. The extended aliasing features of VHDL'93 are not supported.
  14. The groups, reject and postponed features of VHDL'93 are not supported.