This lab has deliverables to be submitted and marked.
Due date: noon, 14 November 2023, Tuesday
Problem Description:
Design and implement a gated SR Latch with positive enable and negative asynchronous preset and clear using NAND gates, and observe its behaviour characteristics.
The characteristic table for the required device is shown below:
preset | clear | enable | S (set) | R (reset) | Next State Q+ | Notes |
0 | 0 | x | x | x | x | Invalid |
0 | 1 | 0 | x | x | 1 | asynchronous set |
1 | 0 | 0 | x | x | 0 | asynchronous reset |
1 | 1 | 0 | x | x | Q | hold (input inactive) |
1 | 1 | 1 | 0 | 0 | Q | hold |
1 | 1 | 1 | 0 | 1 | 0 | synchorous reset |
1 | 1 | 1 | 1 | 0 | 1 | synchorous set |
1 | 1 | 1 | 1 | 1 | x | invalid |
Pre-lab Preparation:
In-Lab Tasks:
(Optionally) take pictures of your circuits and integrate the pictures in your lab report.
The pre-lab preparation and the in-lab tasks can and should be done by a group of up to 2 students.
What to submit (Deliverables):
Lab report (a text or PDF file) that includes all the deliverables except the physically wired circuits, and any accompanying files.
Please clearly identify your tables, diagrams and pictures with meaningful titles in your lab report.
How to submit:
You have two ways to submit:
Submit your lab report (.txt, or .pdf) and pictures (.png files) if any
on any of the cub machines
using the following script:
~liuh/bin/submit 355 Lab7 .
Alternatively, upload your report (and picture if any) to VIU Learn, under CSCI 355's assessment/assignment/Lab 7 tab.