CSCI 355 --- Fall 2023

Lab 4

This lab has deliverables to be submitted and marked.

Due date: noon, 10 October 2023, Tuesday

Problem Description:

Given a 4 bit binary number (w, x, y and z where z is the least significant bit), you are asked to design, implement and simulate a circuit to determine whether the bit string is a valid BCD (8-4-2-1) encoding of a decimal digit, that is, whether the binary number is in the range of 0000 (decimal digit 0) to 1001 (decimal digit 9).

Your task is to design, implement and simulate a logic circuit that takes these 4 binary variables (w, x, y and z) as its input, and outputs a signal of 1 if the inputs represent a valid BCD encoding of any decimal digit, and a signal of 0 otherwise.

Pre-lab Preparation:

1. Draw a truth table consistent with the circuit behaviour specification described in the Problem Description section.
2. Based on the truth table developed in the previous step, write the Boolean function expression in the Sum-of-Products format, then use K-map method to simplify the Boolean function so that minimum logical gates are required to implement the corresponding circuit.
3. Based on your simplified boolean function resulted from the previous step, draw the logic schematic that implements this boolean function.
4. Based on the logic schematic drawn in the previous step, and based on the available types of the chips in our lab, list the chips needed to realize your schematic design.
   Hint: use either (AND (7408), OR (7432) and Inverter (7404)) or (NAND (7400, 7410, 7413)), or (NOR (7402)).
5. For each type of chip used in your implementation, get familiar with its pin information from its datasheet.
6. For each chip used in your circuit, provide a complete pin-out sheet.

In-Lab Tasks:

1. Present your pre-lab preparation to the instructor;
2. If your preparation is approved, wire your circuit;
3. Test your circuit; observe and record the output of your circuit;
4. Demonstrate your circuit to your instructor if it has the correct behaviour and sign off.

(Optionally) take pictures of your circuit and integrate the pictures in your lab report.

The pre-lab preparation and the in-lab tasks can and should be done by a group of up to 2 students.

For the verilog simulation:

Write two Verilog source code files that simulate your designed circuit structurally and behaviourally respectively.

Both your Verilog modules (one structural and the other behavioural) must be tested and verified (using the resulting wave form) on a bench. You lose all marks associated with Verilog simulation if there is any syntax error in your code, and lose partial marks if the behaviour of your module(s) doesn't match with the specification.

What to submit (Deliverables):

1. Lab report (a text or PDF file) that should include at least following sections:
   • Task specification;
   • Truth table;
   • Boolean function for the output in the Sum-of-Product format, its K-map and its equivalent simplified expression;
   • Schematic of the circuit that implements the function;
   • List of resources needed (chips);
   • Pin-out table for each chip used in your circuit;
   • Expected and observed results of each test you performed to test your circuit;
2. Two Verilog source code files, one structural and the other behavioural.

How to submit:

You have two ways to submit:

Put all the files you want to submit, the lab report (.txt, or .pdf), and any picture file(s) clearly named and referenced in your lab report file, to one directory on any of the cub machines, then run the following script in the same directory:
~liuh/bin/submit 355 Lab4 .

Alternatively, upload all the files you want to submit to VIU Learn, under CSCI 355's assessment/assignment/Lab 4 tab.