CSCI 355 --- Fall 2023

Lab 2

This lab has deliverables to be submitted and marked.

Due date: noon, 26 September 2023, Tuesday

Problem Description:

NAND gate (with 2 input and of course 1 output) is a logical gate whose output is false only if both its inputs are true. In other words, NAND gate's output is complement to that of an AND gate. NAND gate's symbol is shown below:

NAND gate is considered to be a universal gate because any other type of gates can be implemented by using NAND gates only.

Tasks:

1. With both verilog code and circuit that use NAND gate(s) only, implement one 2-input AND gate. That is, in your circuit and verilog code, only NAND gate(s) (and its verilog library function) are used and the circuit's (module's) behaviour should be identical to an AND gate with 2 inputs.
2. With both verilog code and circuit that use NAND gate(s) only, implement one 2-input OR gate. That is, in your circuit and verilog code, only NAND gate(s) (and its verilog function) are used and the circuit's (module's) behaviour should be identical to an OR gate with 2 inputs.

Pre-lab Preparation:

The chip to be used in this lab is one 14-pin quad 2-input NAND gate (SN7400). You can find this chip's datasheet online here: https://www.ti.com/lit/ds/symlink/sn74ls00.pdf?ts=1694687564294&ref_url=https%253A%252F%252Fen.wikipedia.org%252F. Read especially the section of Pin Function table to get yourself familiar with the chip's layout.

For task 1, the schematic diagram is shown below:

create and fill the pin-out table for this circuit.

For task 2, the schematic diagram is shown below:

create and fill the pin-out table for this circuit.

In-Lab Tasks:

Wire 2 circuits, one for each task, using the Lab Evaluator, breadboard, one SN7400 chip and wires.

Test your circuits, and demonstrate your circuits to the instructor. Fill the following observation table for each of the circuits. (Note that only the header of the two tables are shown.) These two observation tables should be integrated to your lab report.

(Optionally) take pictures of your circuits and integrate the pictures in your lab report.

The pre-lab preparation and the in-lab tasks can and should be done by a group of up to 2 students.

For the verilog simulation:

Develop two verilog modules using structural method to implement the AND gate and OR gate respectively using only NAND gate. You can view "nand" as a library function that implements the NAND gate where the first parameter is the output of the gate and the other two parameters represent the two inputs to the gate.

The interface of the two modules are provided in here:implementUsingNAND.v. And if you use the provided interface of the two modules, then here is the test bench verilog file that tests both modules.

What to submit (Deliverables):

1. Lab report; a text or PDF file that follows the lab report standard we discussed in the first lab. Include your name and indicate your group partner's name in your lab report.
2. Verilog source code file(s) of the two structural modules.

How to submit:

You have two ways to submit:

Put all the files you want to submit, the lab report (.txt, or .pdf), the verilog source code file(s) (.v), and optionally the picture file(s) (.png), to one directory on any of the cub machines, then run the following script in the same directory:
~liuh/bin/submit 355 Lab2 .

Alternatively, upload all the files you want to submit to VIU Learn, under CSCI 355's assessment/assignment/Lab 2 tab.